function chtex(opt)
{
	var tt,ii,oo,mg;
	switch (opt)
	{
		case "1":
		tt=document.getElementById("ff").innerHTML="What We Provide";
		ii=document.getElementById("gg").innerHTML="<b>Firenza</b> provides state of the art Memory compilers, Memory synthesis tools and design services with a unique feature of optimizing area, power and speed.";
		oo=document.getElementById("oo").innerHTML="<li>SRAMS</li><li>dual port OR 1r1w</li><li>Multiport Register Files</li><li>CAMs</li><li>ROMs</li>	";
		document.getElementById("designflow").style.visibility="hidden";
		break;
		
		case "2":
		tt=document.getElementById("ff").innerHTML="All in One Memory Solution";
		ii=document.getElementById("gg").innerHTML="All the memory structures on the chip are designed and verified with the same flow and methodology yielding consistent design";
		oo=document.getElementById("oo").innerHTML="";
		document.getElementById("designflow").style.visibility="hidden";
		break;

		case "3":
		tt=document.getElementById("ff").innerHTML="Dual Power Supply";
		ii=document.getElementById("gg").innerHTML="All the memory structures can be designed with an option for dual power supply thus maintaining on the fly need based power performance spec while ensuring the stability and retention of the memory in low power mode.";
		oo=document.getElementById("oo").innerHTML="";
		document.getElementById("designflow").style.visibility="hidden";
		break;
	
		case "4":
		tt=document.getElementById("ff").innerHTML="DVFS";
		ii=document.getElementById("gg").innerHTML="With more emphasis on power consumption these days, DVFS (Dynamic Voltage and Frequency Scaling) is essential for power conscious designs. All of our memory structures support DVFS with and without dual power supplies.";
		oo=document.getElementById("oo").innerHTML="";
		document.getElementById("designflow").style.visibility="hidden";
		break;

		case "5":
		tt=document.getElementById("ff").innerHTML="Deep Sleep Mode";
		ii=document.getElementById("gg").innerHTML="All memory structures come with an option of having a deep sleep mode. When deactivated, the static power of the memory goes down to a near zero value.";
		oo=document.getElementById("oo").innerHTML="";
		document.getElementById("designflow").style.visibility="hidden";
		break;

		case "6":
		tt=document.getElementById("ff").innerHTML="Ultra Configurable";
		ii=document.getElementById("gg").innerHTML="Current memory compiler solutions offer precomposed black box type of solutions which do not give the user much option to optimize for Area vs Power vs Performance (APP). Our compilers offer a multitude of solutions with a very fine granularity for choosing the right design for  trade off between APP. Listed below are some of the configuration knobs.";
		oo=document.getElementById("oo").innerHTML="<li>area : Upper and Lower limits</li><ul><li> OR x/y dimension </li></ul><li>Active Power: Upper and lower limit</li><li>Static power : Upper and lower limit</li><li>Frequency:     Upper and lower limit for every operating voltage</li>";
		document.getElementById("designflow").style.visibility="hidden";
		break;

		case "7":
		tt=document.getElementById("ff").innerHTML="Post Silicon Margining bits";
		ii=document.getElementById("gg").innerHTML="Post silicon margin bits to enable maximizing of yield due to skewed process lots. These bits can also be set to maximize performance on fast lots.";
		oo=document.getElementById("oo").innerHTML="";
		document.getElementById("designflow").style.visibility="hidden";
		break;
		
		case "8":
		tt=document.getElementById("ff").innerHTML="Standard features";
		ii=document.getElementById("gg").innerHTML="Customers have a choice of the following standard options for memories";
		oo=document.getElementById("oo").innerHTML="<li>Repair Redundancy,</li><li>Scan</li><li>Bist</li>";
		document.getElementById("designflow").style.visibility="hidden";
		break;

		case "9":
		tt=document.getElementById("ff").innerHTML="Memory synthesis tools";
		ii=document.getElementById("gg").innerHTML="iMDT (Interactive Memory Development Toolkit) is the suite of tools that constitutes the entire memory synthesis flow.<br><b><a href=/pages/products/imdt>iMDT</a></b> components";
		oo=document.getElementById("oo").innerHTML="<li><b><a href=/pages/products/itess>iTESS</a></b>: A memory compiler that delivers layout, netlist, verilog, abstract, LEF etc</li><li><b><a href=/pages/products/itime>iTIME</a></b>: A statistical static timing analysis tool that delivers static timing results, including marginsp.</li><li><b><a href=/pages/products/ichar>iCHAR</a></b>: Cell characterizer, timing view generator and critical path analyzer</li><li><b><a href=/pages/products/ilink>iLINK</a></b>: Schematic editor</li><li><b>iNOISE</b>: Noise Analysis Tool</li><li><b><a href=/pages/products/cms>iVIEW</a></b>: Graphical Stimulus generator, Trends viewer transient waveform viewer</li><li><b>iPOWER</b>: Power optimizer.</b></li>";
		document.getElementById("designflow").style.visibility="visible";
		break;
	
		case "10":
		tt=document.getElementById("ff").innerHTML="Design Services";
		ii=document.getElementById("gg").innerHTML="<b>Firenza.</b> offers top to bottom design services for all IC needs.<br>Designs will always be delivered with the highest APP figure of merit and with plug and play, industry standard views for easy integration.<br> Below is a list of domain expertise for which Design Services can be rendered";
		oo=document.getElementById("oo").innerHTML="<b>Memories</b><li>SRAMS</li><li>dual port OR 1r1w</li><li>Multiport Register Files</li><li>CAMs</li><li>ROMs</li><li>Standard cell development for use in iMDT suite.</li><b>I/O Interfaces</b><li>DDR 1,2,3 system design and verification.</li><li>High speed Serial Interfaces design and verification.</li><li>Full system signal integrity verification.</li><b>Data Path</b><li>Adders, multipliers, ECC etc.</li>";
		document.getElementById("designflow").style.visibility="hidden";
		break;
	}
		
}